CS 2354—ADVANCED COMPUTER ARCHITECTURE previous year questions

Anna University

B.E./B.Tech. DEGREE EXAMINATION

Sixth Semester

Computer Science and Engineering

CS 2354—ADVANCED COMPUTER ARCHITECTURE

(Regulation 2008)

APRIL/MAY 2011

PART A

1. What is loop unrolling? and what are its advantages?

2. Differentiate between static and dynamic branch prediction approaches.

3. What is fine-grained multithreading and what is the advantage and disadvantages of fine-grained multithreading?

4. What a VLIW processor?

5. What is sequential consistency?

6. State the advantages of threading.

7. Differentiate between write-through cache and snoopy cache.

8. Compare SDRAM with DRAM.

9. What is multi–core processor and what are the application areas of multi-core processors?

10. What is a Cell Processor?

PART B

11. (a) Briefly describe any techniques to reduce the control hazard stalls. (16)

Or

(b) (i) Discuss about any two compiler techniques for exposing ILP in

detail. (8)

(ii) Explain how ILP is achieved using dynamic scheduling. (8)

12. (a) (i) Describe the architectural features of IA 64 Processors in detail. (10)

(ii) Explain the architecture of a typical VLIW processor in detail. (6)

or

(b) (i) Describe the architectural features of Itanium Processor. (10)

(ii) Explain how instruction level parallelism is achieved in EPIC

processor. (6)

13. (a) (i) Describe the basic structure of a centralized shared-memory multiprocessor

in detail. (6)

(ii) Describe the implementation of directory-based cache coherence

protocol. (10)

Or

(b) (i) What are the advantages and disadvantages of distributed-memory

Multiprocessors? Describe the basic structure of a distributedmemory multiprocessor

in detail. (8)

(ii) Describe sequential and relaxed consistency model. (8)

14. (a) (i) With suitable diagram, explain how virtual address is mapped to L2 cache

address. (10)

(ii) Discuss about the steps to be followed in designing I/O system. (6)

Or

(b) Describe the optimizations techniques used in compilers to reduce cache miss rate.

(16)

15. (a) (i) Describe the features of SUN CMP architecture in detail. (6)

(ii) What are Multi Core processors? Explain how a multi core

processors works. (10)

Or

(b) (i) Discuss about the SMT kernel structure in detail. (8)

(ii) Describe the architecture of the IBM Cell Processor in detail. (8)

NOVEMBER/DECEMBER 2011.

PART A

1. What is instruction level parallelism?

2. What are the advantages of loop unrolling?

3. What are the limitations of VLIW?

4. What is the use of branch-target buffer?

5. Distinguish between shared memory multiprocessor and messagepassing

multiprocessor.

6. Differentiate multithreading computers from multiprocessor systems

7. Define the terms cache miss and cache hit.

8. What is RAID?

9. What is a multi-core processor?

10. What is a cell processor?

PART B

11. (a) (i) Explain the data and name dependencies with suitable example. (10)

(ii) Discuss about the benefits and limitations of static branch prediction and

dynamic branch prediction (6)

Or

(b) Briefly explain how to overcome data hazards with dynamic scheduling using

Tomasula’s approach. (16)

12. (a) (i) Describe the architecture of Itanium processor with the help of a block

diagram. (8)

(ii) Explain how ILP is achieved in EPIC processors (8)

Or

(b) (i) Describe the architectural features of IA64 processor in detail.(8)

(ii) What are the advantages and disadvantages of software-based and hardwarebased

speculation mechanism? (8)

13. (a) (i) Briefly compare instruction level parallelism with threadlevel

parallelism. (8)

(ii) Explain the basic architecture of a distributed memorymultiprocessor system.

(8)

Or

(b) (i) Explain various memory consistency models in detail. (10)

(ii) What is multithreading and what are the advantages ofmultithreading? (6)

14. (a) What is meant by cache coherence problem? Describe various protocols

for cache coherence. (16)

Or

(b) Briefly explain various I/O performance measures. (16)

15. (a) (i) Describe the architecture of typical CMT processor. (8)

(ii) Discuss the design issues for simultaneous multithreading. (8)

Or

(b) (i) Explain the architectural features of IBM cell processor in detail. (10)

(ii) Briefly compare SMT and CMP architectures. (6)

MAY/JUNE 2013

PART A

1. Define Dynamic Scheduling?

2. List the five level of branch prediction?

3. list loop carried dependences?

4. What is the major disadvantages of supporting apeculation hardware?

5. What is the major disadvantages of using symmetric shared memory.

6. what is consistency?

7. Define the terms cache miss and cache hit.

8. What is the bus master?

9. What are the categories of multi processor?

10. What is fine grained multithreading?

PART B

11. What is instruction-level parallelism? Explain in detail about the varíous

dependence caused in ILP.

Or

(b) Explain how to reduce branch cost with dynamic hardware prediction.

12. Explain how hardware support for exposing more parallelism at compile time.

or

       Explain how hardware based speculation is used to overcome control dependence.

13 .Discuss about the different models for memory consistency.

Or

Define synchronization and explain the different mechanisms employed for synchronization among processors.

14. Explain the various levels of RAID.

0r

Explain the various ways to measure I/O performance.

15. How is multithreading used to exploit thread level parallelism within processor? Explain with example.

Or

Discuss SMT and CMP' architectures  detail.

NOVEMBER/DECEMBER 2012.

PART A

1. Define spatial and temporal locality?

2. What are the advantages of dynamic scheduling using Tomosulo’s Approach?

3. What is ILP and what are the two approaches for ILP?

4. Define casual consistency model?

5. What is loop unrolling and what are the major limitation of loop unrolling?.

6. What is multiprocessor cache coherence             problem?

7. What are the differences and similarities between SCSI and IDE?

8. Compare software and hardware RAID?

9. What is Meant by simultaneous multithreading?

10. What are the advantages of CMP architecture?

PART B

11. (a) i)Discuss about guidelines and principles that are useful in the design and analysis of computer (8)

(ii) Explain dynamic branch prediction (8)

Or

(b) i) Describe the major factor that influences the cost of the computer andf how these factors are changing over time. (8)

ii) Explain hardware based speculation to overcome control dependence (8)

12. (a) (i) Compare CISC, RISC and VLIW. (6)

(ii) Explain VLIW typical architecture with block diagram (10)

Or

(b) (i) Explain basic compiler techniques to exploit ILP.(8)

(ii) Briefly compare hardware and software speculation? (8)

13. (a) (i) What is multithreading and what are the advantages of multithreading?(6).

(ii). Define synchronization and explain the different mechanisms employed for synchronization among processors (10)

Or

(b) (i) Explain the basic architecture of symmetric multiprocessor system with the help of block diagram. (10)

(ii) Describe Coarse grained and fine grained multithreading? (6)

14. (a) Describe the various techniques of optimization of cache in detail. (16)

Or

(b) Briefly Describe levels of RAID. (10)

Describe issues in designing I/O system (6)

15. (a) (i) Describe the various techniques for designing hardware multithreading in detail. (8)

(ii) Explain single chip multiprocessor architecture with the help of architecture. (8)

Or

(b) (i) Explain major challenges and issues in the design of multi core architecture. (16)

May/June 2012

PART A

1. Define ILP
2. Explain Advantages of Dynamic scheduling.
3. What are the advantages and disadvantages of trace scheduling?
4. Whar are the limits on ILP
5. What is multiprocessor cache coherenc?
6. Difference between Coarse grained and fine grained multithreading?
7. Why do DRAMs generally have much larger capacities than SRAMs constructed in the same fabrication technology?
8. What is the average time to read or write a 512sector for a disk? The advertised average seek time is 5ms. The transfer rate is 40 MB/sec. it rotates at 10000RPM, and the controller overhead is 0.1ms. assume the disk is idle so that there is no queuing delay.
9. What is multi core architecture
10. What are the advantage of CPM architecture?

PART B

11. (a) i)Explain various dependences caused in ILP (8)

(ii) Explain static and dynamic branch prediction (8)

Or

(b) i) Explain Tomosulo’s Approach used in dynamic scheduling for over coming data hazards. (8)

ii) Explain How the compiler technology used to improve the performance ILP (8)

12.(a) (i) Explain software pipelining methods to uncover parallelisms . (8)

(ii) Briefly compare hardware and software speculation? (8)

Or

 (b) (i) Discuss the essential features of IA 64 and Itanium processors (16)

     13. (a) (i) Explain the basic architecture of symmetric multiprocessor system with the help

                  of block diagram (8).

(ii). Define synchronization and explain the different mechanisms employed for synchronization among processors (8)

Or

(b) (i) Explain the basic architecture of symmetric multiprocessor system with the help of block diagram consisting of both user and OS activity (8)

(ii) Discuss various memory consistency models? (6)

14. (a) Discuss the various techniques available for reducing cache miss penality. (8)

Briefly Describe levels of RAID. (8)

Or

(b) Write notes on compiler optimization to reduce miss rate. (8)

Describe issues in designing I/O system (8)

15. (a) (i) Explain SMT architecture and its challenges. (8)

(ii) Explain Heterogeneous multicore processors (8)

Or

(b) (i) Explain CMT architecture (8)

ii) Explain IBM cell processor concept in detail (8)